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2.8
Dynamic Electrical Characteristics - Supply and SPI
V L ≤ (V CC - V SS ) ≤ V H , T L ≤ T A ≤ T H , Δ T ≤ 25 K/min, unless otherwise specified
#
Characteristic
Symbol
Min
Typ
Max
Units
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
Quiescent Current Settling Time (Power Applied to Iq = I IDLE ± 2mA)
Reset Recovery Internal Delay (After internal POR)
V CC Micro-cut (C BUF =C REG =C REGA =1 μ F)
Survival Time (V CC disconnect without Reset, C BUF =C REG =C REGA =700 nF)
Survival Time (V CC disconnect without Reset, C BUF =C REG =C REGA =1 μ F)
Reset Time (V CC disconnect above which Reset is guaranteed)
V BUF , Capacitor Monitor Disconnect Time ( Figure 10 )
POR to first Capacitor Test Disconnect
Disconnect Time ( Figure 10 )
Disconnect Delay, Asynchronous Mode ( Figure 10 )
Disconnect Delay, Synchronous Mode ( Figure 11 )
V REG , V REGA Capacitor Monitor
POR to first Capacitor Test Disconnect
Disconnect Time
Disconnect Rate
Serial Interface Timing (See Figure 7 , C DOUT ≤ 80 pF, R DOUT ≥ 10 k Ω )
Clock (SCLK) period (10% of V CC to 10% of V CC )
Clock (SCLK) high time (90% of V CC to 90% of V CC )
Clock (SCLK) low time (10% of V CC to 10% of V CC )
Clock (SCLK) rise time (10% of V CC to 90% of V CC )
Clock (SCLK) fall time (90% of V CC to 10% of V CC )
CS asserted to SCLK high ( CS = 10% of V CC to SCLK = 10% of V CC )
CS asserted to D OUT valid (CS = 10% of V CC to D OUT = 10/90% of V CC )
Data setup time (D IN = 10/90% of V CC to SCLK = 10% of V CC )
D IN Data hold time (SCLK = 90% of V CC to D IN = 10/90% of V CC )
D OUT Data hold time (SCLK = 90% of V CC to D OUT = 10/90% of V CC )
SCLK low to data valid (SCLK = 10% of V CC t o D OUT = 10/90% of V CC )
SCLK low to CS high (SCLK = 10% of V CC to CS = 90% of V CC )
CS high to D OUT disable (CS = 90% of V CC to D OUT = Hi Z)
CS high to CS low (CS = 90% of V CC to CS = 90% of V CC )
t SET
t INT_INIT
t VCC_MICROCUTmin
t VCC_MICROCUT
t VCC_RESET
t POR_CAPTEST
t CAPTEST_TIME
t CAPTEST_ADLY
t CAPTEST_SDLY
t POR_CAPTEST
t CAPTEST_TIME
t CAPTEST_RATE
t SCLK
t SCLKH
t SCLKL
t SCLKR
t SCLKF
t LEAD
t ACCESS
t SETUP
t HOLD_IN
t HOLD_OUT
t VALID
t LAG
t DISABLE
t CSN
?
?
30
50
?
?
?
?
?
?
?
?
320
120
120
?
?
60
?
20
10
0
?
60
?
1000
?
16000 / f OSC
?
?
?
12000 / f OSC
1.5
688 / f OSC
72 / f OSC
12000 / f OSC
6 / f OSC
256 / f OSC
?
?
?
15
15
?
?
?
?
?
?
?
?
?
5
?
?
?
1000
?
5.0
?
?
?
?
?
?
?
?
40
28
?
60
?
?
?
50
?
60
?
ms
s
μ s
μ s
μ s
s
μ s
s
s
s
s
s
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
(3)
(7)
(3)
(3)
(3)
(7)
(7)
(7)
(7)
(7)
(7)
(7)
(9)
(9)
(9)
(9)
(9)
(9)
(9)
(9)
(9)
(9)
(9)
(9)
(9)
(9)
1. Parameters tested 100% at final test.
2. Parameters tested 100% at wafer probe.
3. Verified by characterization
4. * Indicates critical characteristic.
5. Verified by qualification testing.
6. Parameters verified by pass/fail testing in production.
7. Functionality guaranteed by modeling, simulation and/or design verification. Circuit integrity assured through IDDQ and scan testing. Timing
is determined by internal system clock frequency.
8. N/A.
9. Verified by simulation.
10. N/A.
11. Measured at V CC pin; V SYNC guaranteed across full V IDLE range.
12. Self-Test repeats on failure up to a ST_RPT MAX times before transmitting Sensor Error Message.
13. N/A.
14. Thermal resistance between the die junction and the exposed pad; cold plate is attached to the exposed pad.
15. Filter cutoff frequencies are directly dependent upon the internal oscillator frequency.
MMA52xxKW
Sensors
10
Freescale Semiconductor, Inc.
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